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XC4000A Logic Cell Array Family
Product Specifications
Features
Description
The XC4000A family of FPGAs offers four devices at the low end of the XC4000 family complexity range. XC4000A differs from XC4000 in four areas: fewer routing resources, fewer wide-edge decoders, higher output sink current, and improved output slew-rate control.
* Third Generation Field-Programmable Gate Arrays
- - - - - - - - Abundant flip-flops Flexible function generators On-chip ultra-fast RAM Dedicated high-speed carry-propagation circuit Wide edge decoders (two per edge) Hierarchy of interconnect lines Internal 3-state bus capability Eight global low-skew clock or signal distribution network
* The XC4000 routing structure is optimized for smaller
designs, naturally requiring fewer routing resources. The XC4000A devices have four Longlines and four singlelength lines per row and column, while the XC4000 devices have six Longlines and eight single-length lines per row and column. This results in a smaller chip area and lower cost per device.
* Flexible Array Architecture
- Programmable logic blocks and I/O blocks - Programmable interconnects and wide decoders
* XC4000A has two wide-edge decoders on every device
edge, while the XC4000 has four. All other wide-decoder features are identical in XC4000 and XC4000A.
* Sub-micron CMOS Process
- High-speed logic and Interconnect - Low power consumption
* XC4000A outputs are specified at 24 mA, sink current,
while XC4000 outputs are specified at 12 mA. The source current is the same 4 mA for both families.
* Systems-Oriented Features
- - - - IEEE 1149.1-compatible boundary-scan logic support Programmable output slew rate (4 modes) Programmable input pull-up or pull-down resistors 24-mA sink current per output (48 per pair)
* The XC4000A family offers a more sophisticated output
slew-rate control structure with four configurable options for each individual output driver: fast, medium fast, medium slow, and slow. Slew-rate control can alleviate ground-bounce problems when multiple outputs switch simultaneously, and it can reduce or eliminate crosstalk and transmission-line effects on printed circuit boards. Note that the XC4003 and XC4005 devices are available in both flavors, the lower-priced XC4003A/XC4005A with reduced routing, and the higher-priced XC4003/XC4005 with more abundant routing resources. The XC4000A devices are intended for less demanding and more structured designs, and the XC4000 devices for more random designs requiring additional routing resources. The equivalent devices are pin-compatible and are available in identical packages, but they are not bitstream compatible. In order to move from a XC4000A to a XC4000, or vice versa, the design must be recompiled.
* Configured by Loading Binary File
- Unlimited reprogrammability - Six programming modes
* XACT Development System runs on '386/'486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 Series - Interfaces to popular design environments like Viewlogic, Mentor Graphics and OrCAD - Fully automatic partitioning, placement and routing - Interactive design editor for design optimization - 288 macros, 34 hard macros, RAM/ROM compiler
Table 1. The XC4000A Family of Field-Programmable Gate Arrays Device Appr. Gate Count CLB Matrix Number of CLBs Number of Flip-Flops Max Decode Inputs (per side) Max RAM Bits Number of IOBs XC4002A 2,000 8x8 64 256 24 2,048 64 XC4003A 3,000 10 x 10 100 360 30 3,200 80 XC4004A 4,000 12 x 12 144 480 36 4,608 96 XC4005A 5,000 14 x 14 196 616 42 6,272 112
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XC4000A Logic Cell Array Family
Absolute Maximum Ratings Symbol Description VCC VIN VTS Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to + 150 + 260 + 150 Units V V V C C C
TSTG Storage temperature (ambient) TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) TJ
Note:
Junction temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions Symbol VCC Description Supply voltage relative to GND Commercial 0C to 85C junction Supply voltage relative to GND Industrial -40C to 100C junction Supply voltage relative to GND VIH VIL TIN Military -55C to 125C case Min 4.75 4.5 4.5 2.0 0 Max 5.25 5.5 5.5 VCC 0.8 250 Units V V V V V ns
High-level input voltage (XC4000 has TTL-like input thresholds) Low-level input voltage (XC4000 has TTL-like input thresholds) Input signal transition time
At junction temperatures above those listed as Operating conditions, all delay parameters increase by 0.35% per C.
DC Characteristics Over Operating Conditions Symbol VOH VOL ICCO IIL CIN IRIN IRLL Description High-level output voltage @ IOH = -4.0 mA, VCC min Low-level output voltage @ IOL = 24 mA, VCC min (Note 1) Quiescent LCA supply current (Note 2) Leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) Horizontal Long Line pull-up (when selected) @ logic Low 0.02 0.2 -10 Min 2.4 0.4 10 +10 15 0.25 2.5 Max Units V V mA A pF mA mA
Note: 1. With 50% of the outputs simultaneously sinking 24 mA. 2. With no output current loads, no active input or longline pull-up resistors, all package pins at VCC or GND, and the LCA configured with a MakeBits tie option.
2-72
Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The following guidelines relflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade Description Full length, both pull-ups, inputs from IOB I-pins Symbol TWAF Device XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A
-6 Max 8.5 9.0 9.5 10.0 11.5 12.0 12.5 13.0 8.5 9.0 9.5 10.0 11.5 12.0 12.5 13.0
-5 Max 7.5 8.0 8.5 9.0 10.5 11.0 11.5 12.0 7.5 8.0 8.5 9.0 10.5 11.0 11.5 12.0
PRELIMINARY
-4 Max 5.0 6.0 7.0 8.0 6.0 7.0 8.0 9.0 Max 5.7 5.8 5.9 6.0 6.7 6.8 6.9 7.0 Max
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Full length, both pull-ups inputs from internal logic
TWAFL
Half length, one pull-up inputs from IOB I-pins
TWAO
Half length, one pull-up inputs from internal logic
TWAOL
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID) and output delay (one of 4 modes), as listed on page 2-70.
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description Global Signal Distribution From pad through primary buffer, to any clock k
Symbol TPG
Device XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A
Max 7.7 7.8 7.9 8.0 8.7 8.8 8.9 9.0
PRELIMINARY
5.1 5.5 6.3 6.7
Speed Grade
-6
-5
-4
Units ns ns ns ns ns ns ns ns
From pad through secondary buffer, to any clock k
TSG
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XC4000A Logic Cell Array Family
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade Description TBUF driving a Horizontal Longline (L.L.) I going High or Low to L.L. going High or Low, while T is Low, i.e. buffer is constantly active Symbol TIO1 Device XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A All devices XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A
-6 Max 8.2 8.8 9.4 10.0 8.7 9.3 9.9 10.5 10.1 10.7 11.4 12.0 3.0 23.0 24.0 25.0 26.0 10.5 11.0 11.5 12.0
-5 Max 6.0 6.2 6.6 7.0 6.5 6.7 7.1 7.5 8.4 9.0 9.5 10.0 2.0 19.0 20.0 21.0 22.0 8.5 9.0 9.5 10.0
-4 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
I going Low to L.L. going from resistive pull-up High to active Low, (TBUF configured as open drain)
TIO2
T going Low to L.L. going from resistive pull-up or floating High to active Low, (TUBF configured as open drain) T going High to TBUF going inactive, not driving L.L. T going High to L.L. going from Low to High, pulled up by a single resistor
TON
TOFF TPUS
T going High to L.L. going from Low to High, pulled up by two resistors
TPUF
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PRELIMINARY
4.4 5.5 5.0 6.0 7.2 8.0 1.8 14.0 16.0 7.0 8.0
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly. and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy between these two methods, the directly tested values listed below should be used, and the derived values should be ignored.
Speed Grade Description Global Clock to Output (fast) Symbol TICKOF (Max) Global Clock to Output (slew limited) TICKO (Max) Input Set-up Time, using IFF (no delay) TPSUF (Min) Input Hold time, using IFF (no delay) TPHF (Min) Input Set-up Time, using IFF (with delay) TPSU (Min) Input Hold Time, using IFF (with delay) TPH (Min) Device
-6
-5
-4 Units
XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A
21.8 21.5 21.2 21.0 0 0 0 0
18.8 18.5 18.2 18.0 0 0 0 0
PRELIMINARY
11.6 12.0 14.6 15.0 1.6 1.2 4.0 4.5 12.0 12.0 0 0
X6091
XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A XC4002A XC4003A XC4004A XC4005A
14.9 15.1 15.3 15.5 19.9 20.1 20.3 20.5 2.6 2.4 2.2 2.0 4.9 5.1 5.3 5.5
12.2 12.5 12.8 13.0 15.2 15.5 15.8 16.0 2.3 2.0 1.7 1.5 3.7 4.0 4.3 4.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Input Set-Up & Hold Time
IFF TPG Global Clock-to-Output Delay
OFF
* * * * *
X3192
Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). When testing fast outputs, only one output switches. When testing slew-rate limited outputs, half the number of outputs on one side of the device are switching. These parameter values are tested and guaranteed for worst-case conditions of supply voltage and temperature, and also with the most unfavorable clock polarity choice.
TPDLI for -4 Speed Grade
Pad to I1, I2 via transparent latch, with delay
See page 2-76
TPICKD for -4 Speed Grade
Input set-up time pad to clock (IK) with delay XC4003A 15.6 ns XC4005A 15.9 ns
XC4003A 17.6 ns XC4005A 17.9 ns
PRELIMINARY
PRELIMINARY
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XC4000A Logic Cell Array Family
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A XC4005A
-6 Description INPUT Propagation Delays Pad to I1, I2 Pad to I1, I2, via transparent latch (no delay) Pad to I1, I2, via transparent latch (with delay) Clock (IK) toI1, I2, (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) Set-up Time (Note 3) Pad to Clock (IK), no delay Pad to Clock (IK) with delay Hold Time (Note 3) Pad to Clock (IK), no delay Pad to Clock (IK) with delay OUTPUT Propagation Delays Clock (OK) to Pad (fast) Output (O) to Pad (fast) 3-state to Pad begin hi-Z (slew-rate independent) 3-state to Pad active and valid (fast) Additional Delay For medium fast outputs For medium slow outputs For slow outputs Set-up and Hold Times Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High or Low time Global Set/Reset Delay from GSR net through Q to I1, I2 Delay from GSR net to Pad GSR width* TOOK TOKO TCH/TCL TRRI TRPO TMRW 8.0 0.0 5.0 14.5 18.0 21.0 Symbol Min Max
-5 Min Max
-4 Min Max Units
TPICK TPICKD TIKPI TIKPID
7.0 25.0 1.0 neg
6.0 24 .0 1.0 neg
4.0 **
PRELIMINARY
6.5 5.5 6.5 9.5 1.0 2.0 3.0 5.5 0 4.0 13.5 14.6
TPID TPLI TPDLI TIKRI TIKLI
4.0 8.0 26.0 8.0 8.0
3.0 7.0 24.0 7.0 7.0
2.8 6.0 ** 6.0 6.0
ns ns ns ns ns ns ns ns ns
1.0 neg
TOKPOF TOPF TTSHZ TTSONF
7.5 9.0 9.0 13.0 2.0 4.0 6.0 6.0 0.0 4.0
7.0 7.0 7.0 10.0 1.5 3.0 4.5
ns ns ns ns ns ns ns ns ns ns ns ns ns
13.5 17.0 18.0 18.0
* Timing is based on the XC4005. For other devices see XACT timing calculator. ** See preceding page. Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source. 3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time, subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero. Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero, provided the input clock uses the Global signal distribution from pad to IK.
2-76
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A XC4005A
Speed Grade Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H' to X/Y outputs C inputs via H' to X/Y outputs CLB Fast Carry Logic Operand inputs (F1,F2,G1,G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1,F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators. Sequential Delays Clock K to outputs Q Set-up Time before Clock K F/G inputs F/G inputs via H' C inputs via H1 C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F'/G' CIN input via F'/G' and H' Hold Time after Clock K F/G inputs F/G inputs via H' C inputs via H1 C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Master Set/Reset* Width (High or Low) Delay from Global Set/Reset net to Q Symbol
-6 Min Max
-5 Min Max
-4 Min Max Units
TILO TIHO THHO
6.0 8.0 7.0
4.5 7.0 5.0
4.0 6.0 4.5
ns ns ns
TCKO
5.0
3.0
PRELIMINARY
3.0 7.0 28.0
TOPCY TASCY TINCY TSUM TBYP
7.0 8.0 6.0 8.0 2.0
5.5 6.0 4.0 6.0 1.5
5.0 5.5 3.5 5.5 1.5
ns ns ns ns ns
ns
TICK TIHCK THHCK TDICK TECCK TRCK
6.0 8.0 7.0 4.0 7.0 6.0 8.0 10.0
4.5 6.0 5.0 3.0 4.0 4.5 6.0 7.5
4.5 6.0 5.0 3.0 3.0 4.0 5.5 7.3
ns ns ns ns ns ns ns ns
TCKI TCKIH TCKHH TCKDI TCKEC TCKR
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
ns ns ns ns ns ns
TCH TCL
5.0 5.0
4.0 4.0
4.0 4.0
ns ns
TRPW TRIO
5.0 9.0
4.0 8.0
4.0
ns ns
TMRW TMRQ
21.0 33.0
18.0 31.0
18.0
ns ns
* Timing is based on the XC4005. For other devices see XACT timing calculator.
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XC4000A Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A XC4005A
CLB RAM OPTION Description Write Operation Address write cycle time Write Enable pulse width (High) Address set-up time before beginning of WE Address hold time after end of WE DIN set-up time before end of WE DIN hold time after end of WE
Speed Grade Symbol 16 x 2 32 x 1 16 x 2 32 x 1 16 x 2 32 x 1 16 x 2 32 x 1 16 x 2 32 x 1 both TWC TWCT TWP TWPT TAS TAST TAH TAHT TDS TDST TDHT Min
-6 Max
-5 Min Max 8.0 8.0 4.0 4.0 2.0 2.0 2.0 2.0 4.0 5.0 2.0
-4
Min Max Units 8.0 8.0 4.0 4.0 2.0 2.0 2.0 2.0 4.0 5.0 2.0 ns ns ns ns ns ns ns ns ns ns ns
Read Operation Address read cycle time Data valid after address change (no Write Enable) Read Operation, Clocking Data into Flip-Flop Address setup time before clock K Read During Write Data valid after WE going active (DIN stable before WE) Data valid after DIN (DIN change during WE) Read During Write, Clocking Data into Flip-Flop WE setup time before clock K Data setup time before clock K
16 x 2 32 x 1 16 x 2 32 x 1
TRC TRCT TILO TIHO
7.0 10.0 6.0 8.0
5.5 7.5 4.5 7.0
5.0 7.0
PRELIMINARY
4.0 6.0 9.0 11.0 8.5 11.0
9.0 9.0 5.0 5.0 2.0 2.0 2.0 2.0 4.0 5.0 2.0
ns ns ns ns
16 x 2 32 x 1 16 x 2 32 x 1 16 x 2 32 x 1
TICK TIHCK TWO TWOT TDO TDOT
6.0 8.0 12.0 15.0 11.0 14.0
4.5 6.0 10.0 12.0 9.0 11.0
4.5 6.0
ns ns ns ns ns ns
16 x 2 32 x 1 16 x 2 32 x 1
TWCK TWCKT TDCK TDCKT
12.0 15.0 11.0 14.0
10.0 12.0 9.0 11.0
9.5 11.5 9.0 11.0
ns ns ns ns
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-78
CLB RAM Timing Characteristics
T RC ADDRESS
WRITE
WRITE ENABLE
TAS
T WP
T AH
T DS DATA IN REQUIRED
T DH
READ
X,Y OUTPUTS VALID
TILO VALID
READ, CLOCKING DATA INTO FLIP-FLOP
TICK CLOCK T CKO XQ,YQ OUTPUTS VALID (OLD) VALID (NEW) TCH
READ DURING WRITE
T WP WRITE ENABLE T DH DATA IN (stable during WE) T WO X,Y OUTPUTS VALID VALID
DATA IN (changing during WE)
OLD T WO T DO VALID (OLD)
NEW
X,Y OUTPUTS
VALID (PREVIOUS)
VALID (NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
T WP WRITE ENABLE TWCK T DCK DATA IN
CLOCK T CKO XQ,YQ OUTPUTS
X2640
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XC4000A Logic Cell Array Family
2-80
XC4002A Pinouts
Pin Description VCC I/O (A8) I/O (A9) - - I/O (A10) I/O (A11) - I/O (A12) I/O (A13) - - I/O (A14) SGCK1 (A15, I/O) VCC GND PGCK1 (A16, I/O) I/O (A17) - - I/O (TDI) I/O (TCK) - I/O (TMS) I/O - - I/O I/O GND VCC I/O I/O - - I/O I/O I/O I/O - Bound PC84 PQ100 VQ100 PG120 Scan 2 3 4 - - 5 6 - 7 8 - - 9 10 11 12 13 14 - - 15 16 - 17 18 - - 19 20 21 22 23 24 - - 25 26 27 - - 92 93 94 95* 96* 97 98 - 99 100 - - 1 2 3 4 5 6 - - 7 8 - 9 10 - 11* 12 13 14 15 16 17 18* - 19 20 21 22 - 89 90 91 92* 93* 94 95 - 96 97 - - 98 99 100 1 2 3 - - 4 5 - 6 7 - 8* 9 10 11 12 13 14 15* - 16 17 18 19 - G3 G1 F1 E1* F2* F3 D1 E2* C1 D2 E3* B1* C2 D3 C3 C4 B2 B3 A1* A2* C5 B4 A3* B5 A4 C6* A5* B6 A6 B7 C7 A7 A8 A9* B8* C8 A10 B9 A11 B10* - 26 29 - - 32 35 - 38 41 - - 44 47 - - 50 53 - - 56 59 - 62 65 - - 68 71 - - 74 77 - - 80 83 86 89 - Pin Description I/O SGCK2 (I/O) O (M1) GND I (M0) VCC I (M2) PGCK2 (I/O) I/O (HDC) - - I/O I/O (LDC) I/O I/O - - I/O I/O (ERR, INIT) VCC GND I/O I/O - - I/O I/O I/O I/O - - I/O SGCK3 (I/O) GND DONE VCC
PROG
Bound PC84 PQ100 VQ100 PG120 Scan 28 29 30 31 32 33 34 35 36 - - - 37 38 39 - - 40 41 42 43 44 45 - - 46 47 48 49 - - 50 51 52 53 54 55 56 57 - 23 24 25 26 27 28 29 30 31 - - 32 33 34 35 36* 37* 38 39 40 41 42 43 44* 45* 46 47 48 49 - - 50 51 52 53 54 55 56 57 - 20 21 22 23 24 25 26 27 28 - - 29 30 31 32 33* 34* 35 36 37 38 39 40 41* 42* 43 44 45 46 - - 47 48 49 50 51 52 53 54 - C9 A12 B11 C10 C11 D11 B12 C12 A13 B13* E11* D12 C13 E12 D13 F11* E13* F12 F13 G12 G11 G13 H13 J13* H12* H11 K13 J12 L13 K12* J11* M13 L12 K11 L11 L10 M12 M11 N13 N12* 92 95 98 - 101 - 102 103 106 - - 109 112 115 118 - - 121 124 - - 127 130 - - 133 136 139 142 - - 145 148 - - - - 151 154 -
Pin Description - I/O (D6) I/O I/O (D5) I/O (CSO) - - I/O (D4) I/O VCC GND I/O (D3) I/O (RS) - - I/O (D2) I/O I/O (D1)
I/O (RCLK-BUSY/RDY)
Bound PC84 PQ100 VQ100 PG120 Scan - 58 - 59 60 - - 61 62 63 64 65 66 - - 67 68 69 70 - - 71 72 73 74 75 76 77 78 - - 79 80 81 82 - - 83 84 1 - 58 59 60 61 62* 63* 64 65 66 67 68 69 70* - 71 72 73 74 - - 75 76 77 78 79 80 81 82 - - 83 84 85 86 87* 88* 89 90 91 - 55 56 57 58 59* 60* 61 62 63 64 65 66 67* - 68 69 70 71 - - 72 73 74 75 76 77 78 79 - - 80 81 82 83 84* 85* 86 87 88 L9 M10 N11 M9 N10 L8* N9* M8 N8 M7 L7 N7 N6 N5* M6* L6 N4 M5 N3 M4* L5* N2 M3 L4 L3 M2 K3 L2 N1 M1* J3* K2 L1 J2 K1 H3* J1* H2 H1 G2 - 157 160 163 166 - - 169 172 - - 175 178 - - 181 184 187 190 - - 193 196 - - - - 2 5 - - 8 11 14 17 - - 20 23 -
- - I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK VCC O (TDO) GND I/O (A0, WS) PGCK4 (I/O,A1) - - I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) - - I/O (A6) I/O (A7) GND
I/O (D7) PGCK3 (I/O) -
* Indicates unconnected package pins.
Contributes only one bit (.i) to the boundary scan register. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 199 = BSCANT.UPD
2-81 This document was created with FrameMaker 4 0 2
XC4000A Logic Cell Array Family
XC4003A Pinouts
Pin Description VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) - I/O (A12) I/O (A13) - - I/O (A14) SGCK1 (A15,I/O) VCC GND PGCK1 (A16, I/O) I/O (A17) - - I/O (TDI) I/O (TCK) - I/O (TMS) I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O - I/O SGCK2 (I/O) O (M1) GND I (M0) VCC I (M2) PGCK2 (I/O) I/O (HDC) - - I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC PC84 2 3 4 - - 5 6 - 7 8 - - 9 10 11 12 13 14 - - 15 16 - 17 18 - - 19 20 21 22 23 24 - - 25 26 27 - - 28 29 30 31 32 33 34 35 36 - - - 37 38 39 - - 40 41 42 VQ100 PQ100 PG120 89 92 G3 90 93 G1 91 94 F1 92 95 E1 93 96 F2 94 97 F3 95 98 D1 - - E2* 96 99 C1 97 100 D2 - - E3* - - B1* 98 1 C2 99 2 D3 100 3 C3 1 4 C4 2 5 B2 3 6 B3 - - A1* - - A2* 4 7 C5 5 8 B4 - - A3* 6 9 B5 7 10 A4 - - C6 8 11 A5 9 12 B6 10 13 A6 11 14 B7 12 15 C7 13 16 A7 14 17 A8 15 18 A9 - - B8 16 19 C8 17 20 A10 18 21 B9 19 22 A11 - - B10* 20 23 C9 21 24 A12 22 25 B11 23 26 C10 24 27 C11 25 28 D11 26 29 B12 27 30 C12 28 31 A13 - - B13* - - E11* 29 32 D12 30 33 C13 31 34 E12 32 35 D13 33 36 F11 34 37 E13 35 38 F12 36 39 F13 37 40 G12 Bound Scan - 32 35 38 41 44 47 - 50 53 - - 56 59 - - 62 65 - - 68 71 - 74 77 80 83 86 89 - - 92 95 98 101 104 107 110 113 - 116 119 122 - 125 - 126 127 130 - - 133 136 139 142 145 148 151 154 - Pin Description GND I/O I/O I/O I/O I/O I/O I/O I/O - - I/O SGCK3 (I/O) GND DONE VCC
PROG
I/O (D7) PGCK3 (I/O) - - I/O (D6) I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O (D1) I/O (RCLK-BUSY/RDY) - - I/O (D0, DIN) SGCK4 (DOUT, I/O) CCLK VCC O (TDO) GND I/O (A0, WS) PGCK4 (A1, I/O) - - I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND
PC84 43 44 45 - - 46 47 48 49 - - 50 51 52 53 54 55 56 57 - - 58 - 59 60 - - 61 62 63 64 65 66 - - 67 68 69 70 - - 71 72 73 74 75 76 77 78 - - 79 80 81 82 - - 83 84 1
VQ100 PQ100 PG120 38 41 G11 39 42 G13 40 43 H13 41 44 J13 42 45 H12 43 46 H11 44 47 K13 45 48 J12 46 49 L13 - - K12* - - J11* 47 50 M13 48 51 L12 49 52 K11 50 53 L11 51 54 L10 52 55 M12 53 56 M11 54 57 N13 - - N12* - - L9* 55 58 M10 56 59 N11 57 60 M9 58 61 N10 59 62 L8 60 63 N9 61 64 M8 62 65 N8 63 66 M7 64 67 L7 65 68 N7 66 69 N6 67 70 N5 - - M6 68 71 L6 69 72 N4 70 73 M5 71 74 N3 - - M4* - - L5* 72 75 N2 73 76 M3 74 77 L4 75 78 L3 76 79 M2 77 80 K3 78 81 L2 79 82 N1 - - M1* - - J3* 80 83 K2 81 84 L1 82 85 J2 83 86 K1 84 87 H3 85 88 J1 86 89 H2 87 90 H1 88 91 G2
Bound Scan - 157 160 163 166 169 172 175 178 - - 181 184 - - - - 187 190 - - 193 196 199 202 205 208 211 214 - - 217 220 223 226 229 232 235 238 - - 241 244 - - - - 2 5 - - 8 11 14 17 20 23 26 29 -
* Indicates unconnected package pins.
Contributes only one bit (.i) to the boundary scan register. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 247 = BSCANT.UPD
2-82
XC4004A Pinouts
Pin Description VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) - - GND - - I/O (A12) I/O (A13) I/O I/O I/O (A14) SGCK1 (A15, I/O) VCC GND PGCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) - - GND - - I/O (TMS) I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O - - GND - - I/O I/O I/O I/O Bound PC84 TQ144 PQ160 PG120 Scan 2 3 4 - - 5 6 - - - - - 7 8 - - 9 10 11 12 13 14 - - 15 16 - - - - - 17 18 - - 19 20 21 22 23 24 - - 25 26 - - - - - 27 - - - 128 129 130 131 132 133 134 135* 136* 137 - - 138 139 140 141 142 143 144 1 2 3 4 5 6 7 - - 8 9* 10* 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25* 26* 27 - - 28 29 30 31 142 143 144 145 146 147 148 149* 150* 151 152* 153* 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8* 9* 10 11* 12* 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27* 28* 29 30* 31* 32 33 34 35 G3 G1 F1 E1 F2 F3 D1 - - E2 - - C1 D2 E3 B1 C2 D3 C3 C4 B2 B3 A1 A2 C5 B4 - - A3 - - B5 A4 C6 A5 B6 A6 B7 C7 A7 A8 A9 B8 C8 A10 - - - - - B9 A11 B10 - - 38 41 44 47 50 53 - - - - - 56 59 62 65 68 71 - - 74 77 80 83 86 89 - - - - - 92 95 98 101 104 107 - - 110 113 116 119 122 125 - - - - - 128 131 134 137 Pin Description I/O SGCK2 (I/O) O (M1) GND I (M0) VCC I (M2) PGCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) - - GND - - I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O - - GND - - I/O I/O I/O I/O I/O SGCK3 (I/O) GND DONE VCC PROG I/O (D7) PGCK3 (I/O) I/O I/O I/O (D6) I/O Bound PC84 TQ144 PQ160 PG120 Scan 28 29 30 31 32 33 34 35 36 - - - 37 - - - - - 38 39 - - 40 41 42 43 44 45 - - 46 47 - - - - - 48 49 - - 50 51 52 53 54 55 56 57 58 32 33 34 35 36 37 38 39 40 41 42 43 44 - - 45 46* 47* 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62* 63* 64 - - 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 36 37 38 39 40 41 42 43 44 45 46 47 48 49* 50* 51 52* 53* 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68* 69* 70 71* 72* 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89* C9 A12 B11 C10 C11 D11 B12 C12 A13 B13 E11 D12 C13 - - - - - E12 D13 F11 E13 F12 F13 G12 G11 G13 H13 J13 H12 H11 K13 - - - - - J12 L13 K12 J11 M13 L12 K11 L11 L10 M12 M11 N13 N12 L9 M10 N11 205 201 211 214 217 220 - - - - 223 226 229 232 235 238 - 140 143 146 - 149 - 150 151 154 157 160 163 166 - - - - - 169 172 175 178 181 184 - - 187 190 193 196 199 202 - - - - Pin Description - GND - - I/O (D5) I/O (CSO) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O - - GND - - I/O (D1)
I/O (RCLK-BUSY/RDY)
Bound PC84 TQ144 PQ160 PG120 Scan - - - - 59 60 - - 61 62 63 64 65 66 - - 67 68 - - - - - 69 70 - - 71 72 73 74 75 76 77 78 - - 79 80 - - - - - 81 82 - - - 83 84 1 - 81 82* 83* 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98* 99* 100 - - 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117* - 118 119* 120* 121 122 - 123 124 125 126 127 90* 91 92* 93* 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108* 109* 110 111* 112* 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129* 130* 131 132* 133* 134 135 136* 137 138 139 140 141 - - - - M9 N10 L8 N9 M8 N8 M7 L7 N7 N6 N5 M6 L6 N4 - - - - - M5 N3 M4 L5 N2 M3 L4 L3 M2 K3 L2 N1 M1 J3 K2 L1 - - - - - J2 K1 - H3 J1 H2 H1 G2 - - - - 241 244 247 250 253 256 - - 259 262 265 268 271 274 - - - - - 277 280 283 286 289 292 - - - - 2 5 8 11 14 17 - - - - - 20 23 - 26 29 32 35 -
I/O I/O I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK VCC O (TDO) GND I/O (A0, WS) PGCK4 (I/O,A1) I/O I/O I/O (CS1, A2) I/O (A3) - - GND - - I/O (A4) I/O (A5) - I/O I/O I/O (A6) I/O (A7) GND
* Indicates unconnected package pins.
Contributes only one bit (.i) to the boundary scan register. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 295 = BSCANT.UPD
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XC4000A Logic Cell Array Family
XC4005A Pinouts
Pin Description
VCC I/O (A8) I/O (A9) I/O I/O - - I/O (A10) I/O (A11) I/O I/O GND - - - - I/O (A12) I/O (A13) - I/O I/O I/O (A14) SGCK1 (A15, I/O) VCC - - - - GND - PGCK1 (A16, I/O) I/O (A17) I/O I/O - I/O (TDI) I/O (TCK) - - - - GND I/O I/O I/O (TMS) I/O - - I/O I/O I/O I/O GND VCC I/O I/O I/O I/O - - I/O I/O I/O I/O GND - - - - I/O I/O I/O
PC84
2 3 4 - - - - 5 6 - - - - - - - 7 8 - - - 9 10 11 - - - - 12 - 13 14 - - - 15 16 - - - - - - - 17 18 - - - - 19 20 21 22 23 24 - - - - 25 26 - - - - - - - 27 - -
TQ144 PQ160 PQ208 PG156
128 129 130 131 132 - - 133 134 135 136 137 - - - - 138 139 - 140 141 142 143 144 - - - - 1 - 2 3 4 5 - 6 7 - - - - 8 9 10 11 12 - - 13 14 15 16 17 18 19 20 21 22 - - 23 24 25 26 27 - - - - 28 29 30 142 143 144 145 146 - - 147 148 149 150 151 - - 152* 153* 154 155 - 156 157 158 159 160 - - - - 1 - 2 3 4 5 - 6 7 8* 9* - - 10 11 12 13 14 - - 15 16 17 18 19 20 21 22 23 24 - - 25 26 27 28 29 - - 30* 31* 32 33 34 183 184 185 186 187 188* 189* 190 191 192 193 194 195* 196* 197* 198* 199 200 - 201 202 203 204 205 206* 207* 208* 1* 2 3* 4 5 6 7 - 8 9 10* 11* 12* 13* 14 15 16 17 18 19* 20* 21 22 23 24 25 26 27 28 29 30 31* 32* 33 34 35 36 37 38* 39* 40* 41* 42 43 44 H3 H1 G1 G2 G3 - - F1 F2 E1 E2 F3 - - D1* D2* E3 C1 - C2 D3 B1 B2 C3 - - - - C4 - B3 A1 A2 C5 - B4 A3 A4* - - - C6 B5 B6 A5 C7 - - B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 - - C10 A10 A11 B11 C11 - - A12* - B12 A13 A14
Bound Scan
- 44 47 50 53 - - 56 59 62 65 - - - - - 68 71 - 74 77 80 83 - - - - - - - 86 89 92 95 - 98 101 - - - - - 104 107 110 113 - - 116 119 122 125 - - 128 131 134 137 - - 140 143 146 149 - - - - - 152 155 158
Pin Description
I/O - I/O SGCK2 (I/O) O (M1) GND I (M0) - - - - VCC I (M2) PGCK2 (I/O) I/O (HDC) I/O - I/O I/O I/O (LDC) - - - - GND I/O I/O I/O I/O - - I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O - - I/O I/O I/O I/O GND - - - - I/O I/O I/O I/O I/O SGCK3 (I/O) GND - DONE - - VCC - PROG I/O (D7) PGCK3 (I/O) I/O - I/O I/O(D6)
PC84
- - 28 29 30 31 32 - - - - 33 34 35 36 - - - - 37 - - - - - - - 38 39 - - - - 40 41 42 43 44 45 - - - - 46 47 - - - - - - - 48 49 - - 50 51 52 - 53 - - 54 - 55 56 57 - - - 58
TQ144 PQ160 PQ208 PG156
31 - 32 33 34 35 36 - - - - 37 38 39 40 41 - 42 43 44 - - - - 45 46 47 48 49 - - 50 51 52 53 54 55 56 57 58 59 - - 60 61 62 63 64 - - - - 65 66 67 68 69 70 71 - 72 - - 73 - 74 75 76 77 - 78 79 35 - 36 37 38 39 40 - - - - 41 42 43 44 45 - 46 47 48 49* 50 * - - 51 52 53 54 55 - - 56 57 58 59 60 61 62 63 64 65 - - 66 67 68 69 70 - - 71* 72* 73 74 75 76 77 78 79 - 80 - - 81 - 82 83 84 85 - 86 87 45 - 46 47 48 49 50 51 * 52 * 53* 54* 55 56 57 58 59 - 60 61 62 63* 64* 65 * 66* 67 68 69 70 71 72* 73 * 74 75 76 77 78 79 80 81 82 83 84* 85* 86 87 88 89 90 91* 92* 93* 94* 95 96 97 98 99 100 101 102* 103 104 * 105 * 106 107* 108 109 110 111 - 112 113 C12 - B13 B14 A15 C13 A16 - - - - C14 B15 B16 D14 C15 - D15 E14 C16 E15* D16* - - F14 F15 E16 F16 G14 - - G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 - - K14 L16 M16 L15 L14 - - N16* M15* P16 M14 N15 P15 N14 R16 P14 - R15 - - P13 - R14 T16 T15 R13 - P12 T14
Bound Scan
161 - 164 167 170 - 173 - - - - - 174 175 178 181 - 184 187 190 - - - - - 193 196 199 202 - - 205 208 211 214 - - 217 220 223 226 - - 229 232 235 238 - - - - - 241 244 247 250 253 256 - - - - - - - - 259 262 265 - 268 271
* Indicates unconnected package pins.
Contributes only one bit (.i) to the boundary scan register.
2-84 This document was created with FrameMaker 4 0 2
XC4005A Pinouts (continued)
Pin Descriptions I/O - - - - PC84 - - - - - - - - 59 60 - - - - 61 62 63 64 65 66 - - - - 67 68 - - - - - - - 69 70 - - - 71 72 73 74 - - - - 75 76 77 78 - - - 79 80 - - - - - - - 81 82 - - - - 83 84 1 TQ144 80 - - - - 81 82 83 84 85 - - 86 87 88 89 90 91 92 93 94 95 - - 96 97 98 99 100 - - - - 101 102 103 - 104 105 106 107 108 - - - - 109 110 111 112 113 - 114 115 116 117* - - - 118 119 120 121 122 - - 123 124 125 126 127 PQ160 88 89* 90* - - 91 92 93 94 95 - - 96 97 98 99 100 101 102 103 104 105 - - 106 107 108 109 110 - - 111* 112* 113 114 115 - 116 117 118 119 120 - - - - 121 122 123 124 125 - 126 127 128 129* 130* - - 131 132 133 134 135 - 136* 137 138 139 140 141 PQ208 114 115* 116* 117* 118* 119 120 121 122 123 124* 125* 126 127 128 129 130 131 132 133 134 135 136* 137* 138 139 140 141 142 143* 144* 145* 146* 147 148 149 - 150 151 152 153 154 155* 156* 157* 158* 159 160 161 162 163 - 164 165 166 167* 168* 169* 170* 171 172 173 174 175 176* 177* 178 179 180 181 182 PG156 T13 R12* T12* - - P11 R11 T11 T10 P10 - - R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 - - P7 T5 R6 T4 P6 - - R5* - T3 P5 R4 - R3 P4 T2 R2 P3 - - - - T1 N3 R1 P2 N2 - M3 P1 N1 M2* M1* - - L3 L2 L1 K3 K2 - - K1 J1 J2 J3 H2 Bound Scan 274 - - - - - 277 280 283 286 - - 289 292 295 298 - - 301 304 307 310 - - 313 316 319 322 - - - - - 325 328 331 - 334 337 340 - - - - - - - - 2 5 8 - 11 14 17 - - - - - 20 23 26 29 - - 32 35 38 41 -
GND
I/O I/O I/O (D5) I/O (CS0) - - I/O I/O I/O (D4) I/O
VCC GND
I/O (D3) I/O (RS) I/O I/O - - I/O (D2) I/O I/O I/O
GND
- - - - I/O (D1) I/O (RCLK-BUSY/RDY) I/O - I/O I/O (D0, DIN) SGCK4 (DOUT, I/O) CCLK
VCC
- - - - O (TDO)
GND
I/O (A0,WS) PGCK4 (A1,I/O) I/O - I/O I/O (CS1,A2) I/O (A3) - - - -
GND
I/O I/O I/O (A4) I/O (A5) - - I/O I/O I/O (A6) I/O (A7)
GND Boundary Scan Bit 0 = TDO.T
* Indicates unconnected package pins.
Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 343 = BSCANT.UPD
2-85
XC4000A Logic Cell Array Family
For a detailed description of the device architecture, see pages 2-9 through 2-31. For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55. For detailed lists of package pinouts, see pages 2-57 through 2-81 through 2-85. For package physical dimensions and thermal data, see Section 4.
Ordering Information
Example: Device Type
XC4005A-5 PQ160C
Temperature Range
Speed Grade
Number of Pins
Package Type
Component Availability
PINS TYPE
84
PLAST. PLCC PLAST. PQFP
100
120
144
156
160
164
191
196
208
223
225
240
PLAST. PQFP METAL PQFP
299
METAL PQFP
TOP PLAST. BRAZED CERAM. PLAST. VQFP CQFP PGA TQFP
TOP TOP CERAM PLAST. BRAZED CERAM. BRAZED PLAST. PGA PQFP CQFP PGA CQFP PQFP
METAL CERAM. PLAST. PQFP PGA BGA
CODE
PC84 -6 -5 -4 -10 -6 -5 -4 -6 -5 -4 -6 -5 -4
CI C
PQ100 VQ100 CB100 PG120 TQ144 PG156 PQ160 CB164 PG191 CB196 PQ208 MQ208 PG223 BG225 PQ240 MQ240 PG299
CI C CI C MB CI C MB CIMB C C CI C CI C CI CI C CI CI C CI C CI CI C CI CI C
XC4002A
XC4003A
CI C C CI C CI CI C
CI C C
CI C C
MB
XC4004A
XC4005A
C = Commercial = 0 to +85 C B = MIL-STD-883C Class B
I = Industrial = -40 to +100 C M = Mil Temp = -55 to +125 C Parentheses indicate future product plans
2-86

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